Dr. Chandrajit Pal
Senior Research Officer
School of Computer Science and Electronic Engineering (CSEE)University of Essex
Wivenhoe Park, Colchester, CO4 3SQ, United Kingdom.
Biography
Dr Pal is a Senior Research Officer at the School of Computer Science and Electronic Engineering, University of Essex, UK. In addition, he is a member of the school's Embedded and Intelligent Systems (EIS) Research Group. Before that, he was a National Post-doctoral Fellow (SERB awarded, DST, Govt of India) at IIT Hyderabad, India. He received a PhD in Information Technology from the University of Calcutta. He was awarded the prestigious Presidential DST INSPIRE Fellowship by the Govt of India in 2018 to carry out his doctoral studies. He also worked as a Newton Bhabha Fellow in the School of Electronics and Computer Science department at the University of Southampton, UK in 2016.
His research interests mainly include computer vision and signal processing algorithms, custom computing using FPGAs, embedded systems and hardware/software co-design. Besides his interest in intelligent signal processing algorithms, his research also involves developing energy-efficient heterogeneous architectures to execute deep learning techniques on embedded edge devices with limited resources and latency budgets. His research has resulted in over 40 refereed conference and journal papers, patents and book chapters. Before returning to academic research, Dr Pal worked as an AI Research Engineer and Senior Engineer in the semiconductor industry.
Research Projects
IDEAL: Reducing Carbon Footprints of IoT Devices
2025 - Present | EPSRC Project
Contributing to an EPSRC project "IDEAL: Reducing Carbon Footprints of IoT Devices through Extension of Active Lifespans" in collaboration with the University of Glasgow and the University of Oxford. The IDEAL project aims to drastically extend the active lifespan of Internet of Things (IoT) devices from years to decades. This initiative seeks to reduce the substantial carbon footprint associated with manufacturing ICT devices by enabling them to be repurposed and degrade gracefully through novel hardware design, software co-design, formal methods, and machine learning.
MORELLO-HAT: Morello High-Level API and Tooling
2023 - 2025 | EPSRC DsBD Project
Contributed to an EPSRC project by DsBD named MORELLO-HAT in collaboration with the University of Glasgow and the University of Oxford. The Morello-HAT project intends to create a common API that can be used by compiler developers as well as programmers of higher-level languages, to allow them to leverage Morello's HW capabilities to improve memory security and type safety, spatial as well as temporal, of their language and programs.
Contact
Office Email: chandrajit.pal@essex.ac.uk
Personal Email: palchandrajit@gmail.com